The principles of the present invention have application to various types of non-volatile memories, those currently existing and those contemplated to use new technology being developed. Implementations of the present invention, however, are described with respect to a flash electrically-erasable and programmable read-only memory (EEPROM), wherein the storage elements are floating gates.
A number of architectures are used for non-volatile memories. A NOR array of one design has its memory cells connected between adjacent bit (column) lines and control gates connected to word (row) lines. The individual cells contain either one floating gate transistor, with or without a select transistor formed in series with it, or two floating gate transistors separated by a single select transistor. Examples of such arrays and their use in storage systems are given in the following U.S. patents and pending applications of SanDisk Corporation that are incorporated herein in their entirety by this reference: U.S. Pat. Nos. 5,095,344, 5,172,338, 5,602,987, 5,663,901, 5,430,859, 5,657,332, 5,712,180, 5,890,192, and 6,151,248, and Ser. No. 09/505,555, filed Feb. 17, 2000, and Ser. No. 09/667,344, filed Sep. 22, 2000.
A NAND array of one design has a number of memory cells, such as 8, 16 or even 32, connected in series string between a bit line and a reference potential through select transistors at either end. Word lines are connected with control gates of cells in different series strings. Relevant examples of such arrays and their operation are given in U.S. Pat. No. 6,046,935 and U.S. patent application Serial No. 09/893,277, filed Jun. 27, 2001, that are also hereby in incorporated by reference, and references contained therein.
In non-volatile semiconductor memories, such as an EEPROM or Flash memory, the amount of data stored per memory cell has been increased in order to increase storage densities. At the same time, the operating voltages of such devices have decreased to reduce power consumption. This results in a greater number states stored in a smaller range of voltage or current values. As the voltage or current separation between data states decreases, the accurate placement of the breakpoints used to distinguish between data states becomes more critical. Another complicating factor is that the parameter, such as threshold voltage, representing the data state of the storage element populations can vary with operating conditions. Consequently, in order to maintain the reliability of memory operation in light of the conflicting demands of increasing the number of states per cell and decreasing operating voltages, improvements to memory design become ever more important.
FIG. 1 shows a distribution of threshold voltages for a collection of storage elements programmed into one of four data states for a system designed for 3 volt operations, such as described in U.S. Pat. No. 6,046,935 and U.S. patent application Ser. No. 09/893,277, both incorporated above. The programming process has grouped the memory cells into four populations, labeled as “0”, “1”, “2”, and “3”. The “0” state is characterized by a negative threshold voltage, Vth<0V, with the other states characterized by having threshold voltages above ground. Typically, the following an erase and pre-programming phase, the memory elements are programmed to their respective data states based upon the verify voltages of VCG1V for the “1” state, VCG2V for the “2” state, and VCG3V for the “3” state. The result is the four cell population distributions represented by the lumps in FIG. 1.
During a read process, the data states are distinguished from each other by the breakpoints: VCR3R distinguishes the “3” state from the “2”, VCR2R distinguishes the “2” state from the “1”, and VCR1R distinguishes the “1” state from the “0”. Although the states are defined by their threshold voltages in the exemplary embodiment of a FLASH memory, another parameter, such as current or frequency, may be sensed in a read or verify operation. More detail on read, write, and verify operations are given in the various references incorporated above and in U.S. patent application Ser. No. 10/052/924, filed on Jan. 18, 2002, that is also hereby incorporated by reference, and references contained therein.
To maintain the integrity of both the read and the write process, both the population distributions of cells in the different states and the read points for distinguishing these points need to be well defined. The population distributions can shift over time or as operating conditions (temperature, power supply level, device age, etc.) change. Although the four-state, 3.0V design (corresponding to Vdd=2.6V) may provide a sufficient safety margin in which to place the read points between the state populations, these tolerances can become very tight as systems move to more states, lower operating voltages, or both.